To reduce the 1/f noise of the operational amplifier and the noise caused by mismatch voltages and the like in an integrating circuit, generally the correlated double sampling technology may be introduced. Specifically, different input signals are successively sampled twice, and the input signals upon the twice samplings are subjected to an analogous subtraction, to eliminate the 1/f noise of the operational amplifier and the noise caused by mismatch voltages and the like. In this way, real signal levels are obtained.
An exemplary correlated double sampling integrating circuit includes: a sampling circuit, an energy storage capacitor and an amplifier. The sampling circuit performs time-division based sampling under control of two non-overlap clock signals Φ1 and Φ2. When the clock signal Φ1 is high and the clock signal Φ2 is low, a positive electrode sheet of the energy storage capacitor Ci samples an input signal V1, and meanwhile a negative electrode sheet thereof may sample the 1/f noise of the operational amplifier and the noise caused by mismatch voltages and the like. When the clock signal Φ1 is low and the clock signal Φ2 is high, the positive electrode sheet of the energy storage capacitor Ci samples an input signal V2, and meanwhile the negative electrode sheet thereof may sample the 1/f noise of the operational amplifier and the noise caused by mismatch voltages and the like. If at two contiguous phases, the /f noise of the operational amplifier and the mismatch voltages substantially remain unchanged, with respect to two adjacent sampling time periods, the variation amount of the output voltage of the amplifier is not affected by the 1/f noise and the mismatch voltages, such that /f noise of the operational amplifier and the noise caused by mismatch voltages and the like are eliminated.
However, in the above exemplary correlated double sampling integrating circuit, at the moment the clock signal Φ1 changes from a low level to a high level, the output of the amplifier may transition from an output value when the clock signal Φ2 is a high level to a common-mode voltage Vcm. Likewise, at the moment the clock signal Φ2 changes from a low level to a high level, the output of the amplifier may transition from the common-mode voltage Vcm to a sum of the output value of the original stage of the clock signal Φ2 and an integration value. Consequently, the output jump of the correlated double sampling integrating circuit become greater and greater as the count of integrations increases.